In large digital PCM switching systems, one must monitor the switching system to ensure that it is operating correctly. Because of the large number of PCM channels that may be routed by a relatively small amount of circuitry, the core of the switching system is typically duplicated to provide redundancy so as to increase the availability of the system. Typically, two planes of switching circuitry operate simultaneously, with one plane acting as a hot standby for the other. PCM data from each source is routed to both switching planes and at each destination, circuitry selects PCM data from one of the switching planes, falling back to the other switching plane if required. In order to benefit from this redundancy, one must be able to detect a failure in the active switching plane and quickly switch over to the still functional switching plane while the failed switching plane is taken out of service so that failed circuits can be identified and replaced without affecting service (provided that another fault does not occur in the still functional switching plane while it is operating without a backup). Thus, rapid detection and diagnosis of a fault is required to minimize "downtime" of the PCM switching capability.
In typical PCM switching systems, data to be routed through the switch consists of an 8 bit PCM sample. Such samples are normally presented to the switching system at an 8 kHz rate, and are often grouped into time division multiplexed (TDM) frames carrying multiple PCM sample streams, where the frame repetition rate is 8 kHz. In many cases a lower bit rate channel is routed together with the PCM sample in order to carry signaling information. Modern systems usually allow for four state signaling and, thus require 4 bits to encode the signaling state. With frames being transmitted at 8 kHz there is a 125 microsecond interval between one frame and the next. With a requirement that PCM data be transmitted at a 64 kbit/s rate, this requires transmission of 8 bits every 125 microseconds or, in other words, one 8 bit word every frame. The requirement for signaling throughput is only 1.333 kbit/s in North America and 2 kbit/s in Europe and elsewhere. This means that transmitting only 1 bit per frame of signaling data would be more than adequate. Both requirements could be met by transmitting a 9 bit word every frame with one bit being of signaling data and the other 8 bits being PCM data. In fact, only 4 bits need be sent every 16 to 24 frames (referred to as a multi-frame).
When sending data through a switch core three types of checks are required, namely, a data integrity check, a path integrity check, and a flow integrity check. A data integrity check determines if the data was altered as it passes through the switch core. This is typically accomplished by adding a parity bit to the word of PCM data that is routed through the switch core. Generation and checking of parity is extremely simple. However, a parity bit does not permit path or flow integrity checking.
It is possible for a data path to become altered on occasion and for a given destination to be receiving data from the wrong source. Consequently, it is desirable to do a regular path integrity check. Many switch cores do not incorporate such a check. Those that do often accomplish such a check by adding an extra bit to the word of PCM data that is routed through the switch core to implement a data link. By exchanging messages through this data link, connectivity can be regularly checked. The problem with this approach is that the circuitry to exchange such messages may be quite complex and slow to detect a path integrity failure.
A flow integrity check determines if data continues to flow via the switch core path. Many switch cores do not incorporate such a check. Those that do often accomplish a flow integrity check by adding an extra bit to the word of PCM data that is routed through the switch core. Such an extra bit implements a data link as for the extra bit for the path integrity check discussed above by which messages may be exchanged and flow integrity monitored. Typically, this is accomplished using the same bit as used for the data link. The problem with this approach, as for the path integrity check using an extra bit, is that the circuitry to exchange such messages may be quite complex and slow to detect a flow integrity failure.
Accordingly, it is an object of the invention to provide an improved method and apparatus for checking path and flow integrity. It is a further object of the invention to provide a simple circuit for monitoring path and flow integrity.